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| (R) ISL23710 Volatile Digitally Controlled Potentiometer (XDCPTM) Data Sheet August 22, 2005 FN6126.0 Terminal Voltage 3V or 5V, 128 Taps Up/Down Interface The Intersil ISL23710 is a digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper switches, and a control section. The wiper position is controlled by a Up/Down interface. The potentiometer is implemented by a resistor array composed of 127 resistive elements and a wiper switching network. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the CS, U/D, and INC inputs. The wiper register is volatile and is reset to midscale on power up. The wiper position can be locked while powered up to prevent inadvertent changes. The device can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including: * Industrial and Automotive Control * Parameter and Bias Adjustments * Amplifier Bias and Control Features * Up/Down Interface with Chip Select Enable * DCP Terminal Voltage from 2.7V to 5V * 127 Resistive Elements - Typical RTOTAL tempco 50ppm/C - Ratiometric tempco 4ppm/C - End to end resistance range 20% - Wiper resistance = 70 typ at VCC = 3.3V * Low Power CMOS - V- = -2.7V to -5.5V - VCC = 2.7V to 5.5V - Active current, 1mA max - Standby current, 500nA max * RTOTAL Values = 10k, 50k * Volatile Wiper Storage with Wiper Locking * Packages - 10 Ld MSOP * Pb-Free Plus Anneal Available (RoHS Compliant) Ordering Information PART NUMBER (BRAND) ISL23710WIU10Z (AOG) (Notes 1, 2) ISL23710UIU10Z (AOF) (Notes 1, 2) NOTES: 1. Add "-T" suffix for tape and reel. 2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. RESISTANCE OPTION () 10K 50K TEMP RANGE (C) PACKAGE PKG. DWG. # Pinout ISL23710 (10 LD MSOP) TOP VIEW -40 to +85 10 Ld MSOP M10.118 (Pb-Free) -40 to +85 10 Ld MSOP M10.118 (Pb-Free) U/D VGND CS NC 1 2 3 4 5 10 9 8 7 6 INC VCC RL RW RH 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil, Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL23710 Block Diagram U/D VVCC INC CS UP/DOWN (U/D) INCREMENT (INC) DEVICE SELECT (CS) RL RECALL CONTROL CIRCUITRY INTERFACE AND CONTROL RW ONE OF 128 DECODER 2 GND SIMPLE BLOCK DIAGRAM 1 0 RL RW DETAILED BLOCK DIAGRAM RH 7-BIT UP/DOWN COUNTER 127 126 125 124 TRANSFER GATES RH RESISTOR ARRAY Pin Descriptions PIN NUMBER 1 2 3 4 5 6 7 8 9 10 SYMBOL U/D VGND CS NC RH RW RL VCC INC DESCRIPTION Controls the direction of wiper movement and whether the counter is incremented or decremented. Negative supply voltage for the potentiometer wiper control. Ground. Should be connected to a digital ground. Chip Select. The device is selected when the CS input is LOW. No Connect. Pin is to be left unconnected. A fixed terminal for one end of the potentiometer resistor. The wiper terminal which is equivalent to the movable terminal of a potentiometer. A fixed terminal for one end of the potentiometer resistor. Positive logic supply voltage. Increment input; negative edge triggered. 2 FN6126.0 August 22, 2005 ISL23710 Absolute Maximum Ratings Temperature Under Bias . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on CS, INC, U/D and VCC with Respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3V Voltage on V- (Referenced to GND) . . . . . . . . . . . . . . . . . . . . . . -6V V = |V(RH)-V(RL)| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . . 300C IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V RH, RL, RW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V- to VCC ESD Rating (MIL-STD-883, Method 3015.7) . . . . . . . . . . . . . . .>2kV Thermal Information Thermal Resistance (Typical, Note 1) MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . JA (C/W) 170 Recommended Operating Conditions Temperature Range (Industrial) . . . . . . . . . . . . . . . . .-40C to +85C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7V to -5.5V CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. NOTE: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Analog Specifications SYMBOL RTOTAL Over recommended operating conditions unless otherwise stated. TEST CONDITIONS W option U option MIN TYP (Note 1) 10 50 -20 VV- = -5.5V; VCC = +5.5V, wiper current = (VCC - V-)/RTOTAL 70 10/10/ 25 Voltage at pin from V- to VCC -1 0.1 1 +20 VCC 200 MAX UNIT k k % V pF A PARAMETER RH to RL Resistance RH to RL Resistance Tolerance VRH,VRL RW CH/CL/CW ILkgDCP RH, Rl Terminal Voltage Wiper Resistance Potentiometer Capacitance (Note 13) Leakage on DCP Pins VOLTAGE DIVIDER MODE (0V @ RL; V+ @ RH; measured at RW, unloaded) INL (Note 6) DNL (Note 5) ZSerror (Note 3) FSerror (Note 4) Integral Non-linearity Differential Non-linearity Zero-Scale Error W, U options W option U option Full-Scale Error W option U option DCP register set to i = 16 to 120d, T = -40C to 85C -1 -0.5 0 0 -4 -2 1 0.5 -1 -0.5 4 1 0.5 4 2 0 0 LSB (Note 2) LSB (Note 2) LSB (Note 2) LSB (Note 2) ppm/C TCV Ratiometric Temperature Coefficient (Note 7,13) RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) RINL (Note 11) RDNL (Note 10) Roffset (Note 9) Integral Non-linearity Differential Non-linearity Offset DCP register set to 0d, W option DCP register set to 0d, U option TCR Resistance Temperature Coefficient (Notes 12,13) DCP register set to i = 16 to 127d, T = -40C to +85C DCP register set between 16 and 127d Monotonic over all tap positions -1 -0.5 0 0 2 0.5 50 1 0.5 5 2 MI (Note 8) MI (Note 8) MI (Note 8) MI (Note 8) ppm/C 3 FN6126.0 August 22, 2005 ISL23710 Operating Specifications Over the recommended operating conditions unless otherwise specified. SYMBOL ICC1 IVISB PARAMETER TEST CONDITIONS MIN TYP (Note 1) MAX 500 -100 500 300 -500 -300 -10 2.5 10 UNITS A A nA nA nA nA A V VCC Supply Current, Volatile Write/Read CS = VIL, U/D = VIL or VIH and INC = 0.4V/2.4V min. tCYC RL, RH, RW not connected V- Supply Current, Volatile Write/Read VCC Current (Standby) CS = VIL, U/D = VIL or VIH and INC = 0.4V/2.4V min. tCYC RL, RH, RW not connected VCC = +5.5V, 3 Wire Interface in Standby State VCC = +2.7V, 3 Wire Interface in Standby State IV-SB V- Current (Standby) V- = -5.5V, 3 Wire Interface in Standby State V- = -2.7V, 3 Wire Interface in Standby State ILkgDig Vpor Leakage Current, at Pins INC, CS, U/D, Voltage at pin from GND to VCC A0, and A1 Power-on Recall Voltage Minimum VCC at which the wiper is Reset SERIAL INTERFACE SPECS VIL VIH Hysteresis (Note 13) Cpin (Note 13) INC, CS, and U/D Input Buffer LOW Voltage INC, CS, and U/D Input Buffer HIGH Voltage INC, CS, and U/D Input Buffer Hysteresis INC, CS, and U/D Pin Capacitance -0.3 0.7*VCC 0.15* VCC 10 0.3*VCC VCC+0.3 V V V pF AC Electrical Specifications SYMBOL tCl tlD tDI tlL tlH tICL tIW (Note 13) tCYC tR, tF CS to INC Setup VCC = 5V 10%, TA = Full Operating Temperature Range unless otherwise stated PARAMETER MIN 100 100 1 1 1 1 1 2 500 TYP (Note 1) MAX UNIT ns ns s s s s s s s INC HIGH to U/D Change U/D to INC Setup INC LOW Period INC HIGH Period Lock Setup Time, INC High to CS High INC to RW Change INC Cycle Time INC Input Rise and Fall Time 4 FN6126.0 August 22, 2005 ISL23710 NOTES: 1. Typical values are for TA = 25C and 3.3V supply voltage. 2. LSB: [V(RW)127 - V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 3. ZS error = V(RW)0/LSB. 4. FS error = [V(RW)127 - VCC]/LSB. 5. DNL = [V(RW)i - V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 6. INL = V(RW)i - (i * LSB - V(RW)0) for i = 1 to 127. Max ( V ( RW ) i ) - Min ( V ( RW ) i ) 10 6 7. TC V = ----------------------------------------------------------------------------------------------x ---------------[ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] 2 125C Max( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 8. MI = |R127 - R0| /127. R127 and R0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 9. Roffset = R0/MI, when measuring between RW and RL. Roffset = R127/MI, when measuring between RW and RH. 10. RDNL = (Ri - Ri-1)/MI, for i = 16 to 127d. 11. RINL = [Ri - (MI * i) - R0]/MI, for i = 16 to 127d. 6 [ Max ( Ri ) - Min ( Ri ) ] 10 12. TC = --------------------------------------------------------------- x ---------------R [ Max ( Ri ) + Min ( Ri ) ] 2 125C Max( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the temperature range. 13. This parameter is not 100% tested. Symbol Table WAVEFORM INPUTS Must be steady OUTPUTS Will be steady May change from Low to High May change from High to Low Will change from Low to High Will change from High to Low Don't Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance 5 FN6126.0 August 22, 2005 ISL23710 AC Timing CS tCYC tCI INC tIL tIH tICL 90% 90% 10% tID tDI tF tR U/D tIW RW MI (3) Power Up and Down Requirements In order to prevent unwanted tap position changes, bring the CS and INC high before or concurrently with the VCC pin on power-up. The potentiometer voltages must be applied after this sequence is completed. During power-up, the data sheet parameters for the DCP do not fully apply until 1ms after VCC reaches its final value. The wiper will be set to its initial value (64d) once VCC exceeds VPOR. Chip Select (CS) The device is selected when the CS input is LOW. Principles of Operation There are three sections of the ISL23710: the input control, counter and decode section, and the resistor array. The input control section operates just like an up/down counter. The output of this counter is decoded to turn on a single electronic switch connecting a point on the resistor array to the wiper output. The resistor array is comprised of 127 individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. That is, the counter does not wrap around when clocked to either extreme. The electronic switches on the device operate in a "make before break" mode when the wiper changes tap positions. If the wiper is moved several positions, multiple taps are connected to the wiper for tIW (INC to VW change). The RTOTAL value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions. Pin Descriptions RH and RL The high (RH) and low (RL) terminals of the ISL23710 are equivalent to the fixed terminals of a mechanical potentiometer. The terminology of RL and RH references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal. RW Rw is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the control inputs. Up/Down (U/D) The U/D input controls the direction of the wiper movement and whether the counter is incriminated or decremented. Instructions and Programming The INC, U/D and CS inputs control the movement of the wiper along the resistor array. With CS set LOW the device is selected and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a seven bit counter. The output of this counter is decoded to select Increment (INC) The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the counter in the direction indicated by the logic level on the U/D input. 6 FN6126.0 August 22, 2005 ISL23710 one of one-hundred twenty-eight wiper positions along the resistive array. Bringing CS HIGH after INC is HIGH will cause the wiper value to be locked until power down (further changes in CS and INC will not change the wiper position). Otherwise, INC should be brought HIGH after CS to allow continued wiper changes. The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. During initial power-up CS must go high along with or before VCC to avoid an accidental tap position change. TABLE 1. MODE SELECTION CS L L H H L H H L L INC U/D H L X X X X H L Wiper Up Wiper Down Lock Wiper Value Standby Standby Standby Wiper up One Position (not recommended) Wiper Down One Position (not recommended) MODE 7 FN6126.0 August 22, 2005 ISL23710 Mini Small Outline Plastic Packages (MSOP) N M10.118 (JEDEC MO-187BA) 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 E INCHES SYMBOL MIN 0.037 0.002 0.030 0.007 0.004 0.116 0.116 MAX 0.043 0.006 0.037 0.011 0.008 0.120 0.120 MILLIMETERS MIN 0.94 0.05 0.75 0.18 0.09 2.95 2.95 MAX 1.10 0.15 0.95 0.27 0.20 3.05 3.05 NOTES 9 3 4 6 7 15o 6o Rev. 0 12/02 INDEX AREA -B12 TOP VIEW 0.25 (0.010) GAUGE PLANE SEATING PLANE -C4X R1 R 0.20 (0.008) ABC A A1 A2 b c D E1 4X L L1 e E L 0.020 BSC 0.187 0.016 0.199 0.028 0.50 BSC 4.75 0.40 5.05 0.70 A A2 A1 -He D b 0.10 (0.004) -A0.20 (0.008) C SEATING PLANE L1 N R 0.037 REF 10 0.003 0.003 5o 0o 15o 6o 0.95 REF 10 0.07 0.07 5o 0o C a C L E1 C R1 SIDE VIEW -B- 0.20 (0.008) CD END VIEW NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 FN6126.0 August 22, 2005 |
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